“On the design of Fast IEEE Floating-Point Adders,” by Seidel and Even, IEEE Computer Society, Proceedings of the 15th IEEE Symposium on Computer Arithmetic (ARITH '01) describes a floating point adder design that includes two distinct paths, known as a “far path” and a “near path,” which are well-known in the art of floating point addition units. The near path computes effective subtractions (either an addition instruction in which the two operands have different signs, or a subtraction instruction in which the two operands have the same sign) in which the operands have absolute exponent differences less than or equal to one, and the far path computes all other cases. Each path executes the effective subtraction floating point instruction in parallel, and the final result is primarily selected based on the exponent difference.
In the near path calculation an effective subtraction is performed that may result in elimination of several leading digits of numerical significance, sometimes referred to as “mass cancellation.” Consequently, a resulting most significant digit must then be located and left shifted to produce a normal form representation in a process typically called “normalization.” In this context, it is desirable to predict the number of leading significant digits that will be eliminated by the subtraction. The prediction is performed in parallel with the actual mantissa subtraction and, in comparison to waiting for the true difference bits, substantially accelerates enumeration of any eliminated leading significant digits. Consequently, the entire normalization process is accelerated.
To illustrate, consider the subtraction of a subtrahend B from a minuend A as follows:
A=10110111
B=10110010
A−B=00000101
B−A=11111010 (one's complement representation)
In the case of A−B, mass cancellation of five significant digits occurs leaving a positive result with five leading zeros. In the case of B−A, mass cancellation of five significant digits occurs leaving a negative result with five leading ones or, stated alternatively, with five leading sign digits equal to one. In both cases, the most significant digit is in the third least significant bit position such that a left shift of five bits is required to normalize the difference. As mentioned above, predicting that five leading significant digits will be eliminated by the subtraction may significantly accelerate the normalization.
The concept of leading zeros/ones/sign digits prediction has been much studied, dating to an early published work by Kershaw, et al., “A Programmable Digital Signal Processor with 32-bit Floating-Point Arithmetic,” IEEE Solid State Circuits Conference, Digest of Papers, 1985, pp. 92-93, and substantially summarized by Schmookler and Nowka in “Leading Zero Anticipation and Detection—A Comparison of Methods,” Proceedings of the 15th IEEE Symposium on Computer Arithmetic, 2001. Additional techniques were demonstrated in the Seidel and Even paper mentioned above.
With reference to two inputs, P and Q, to an adder that performs an effective subtraction, it is recognized that a string of leading zeros in the resulting difference may be predicted using a (Z*+T*GZ*) pattern match, where Z* denotes a string of one or more Z, and T* denotes a string of one or more T, and where:Ti=PiXORQi,Gi=PiANDQi,Zi=(!Pi)AND(!Qi),where Pi and Qi are corresponding bits of P and Q, respectively, and Ti, Gi, and Zi are pattern matching function values of Pi and Qi. It is also recognized that a string of leading ones, or leading sign bits equal to one, may be predicted using a (G*+T*ZG*) pattern match.
As Schmookler and Nowka note in section 2:                In most of the literature, the term leading zeros refers to a starting string of zeros prior to the first one, while leading ones refers to a starting string of ones prior to the first zero. However, there may be some confusion since several papers also use the term leading one predictor for determining the first one after a starting string of zeros. Therefore, in this paper, we avoid the use of that term.        
U.S. Pat. No. 6,085,208 to Oberman et al. is entitled: leading one prediction unit for normalizing close path subtraction results within a floating point arithmetic unit. Oberman et al. describe a predictor that predicts the position of a first one bit (i.e., the first significant digit) after a string of leading zeros (i.e., zero or more zeros) in a presumed positive difference of two inputs; hence their use of the term “leading one prediction unit.” Stated alternatively, Oberman et al. describe a leading zeros predictor that provides a prediction string used to predict the number of leading zeros present due to mass cancellation in the presumed positive difference. Therefore, in order to avoid confusion for the reasons stated by Schmookler and Nowka, the present disclosure will use the term “leading zeros prediction unit” to refer to the prediction unit of Oberman et al., rather than the term “leading one prediction unit” used in its title. The leading zeros prediction unit of Oberman et al. provides the prediction for a near path subtractor that performs an effective subtraction of two inputs by assuming the difference between the exponent values of the two inputs is +1 or −1 and ordering the inputs to cause the smaller magnitude input to be effectively subtracted from the larger magnitude input to produce a positive difference result. Ordering the inputs to presume a positive result when the exponent difference is +1 or −1 allowed Oberman et al. to provide a leading zeros prediction unit that is optimized to reduce space requirements and increase performance relative to a prior art predictor that only presumed a positive mantissa difference but did not presume an exponent difference of +1 or −1, which was an improvement over a prior art generalized predictor that made neither presumption.